1. Field
This disclosure pertains to the field of image display, and more particularly, to a method and device for driving a plurality of display devices, and in various embodiments, a method and device for driving a plurality of display devices (e.g., liquid crystal display (LCD) devices) to display a combined image.
2. Description
Among display devices, liquid crystal display devices (LCD) devices are popular for a variety of applications, including in particular portable or mobile devices such as mobile telephones or other communication devices, portable computing devices, etc. In general, a liquid crystal display (LCD) panel includes a pair of substrates provided with pixel electrodes and a common electrode, and a liquid crystal layer with dielectric anisotropy interposed between the substrates. The liquid crystal display device controls the transmittance of light passing through the liquid crystal layer by applying an electric field to the liquid crystal layer and adjusting the field strength for displaying desired images.
FIG. 1 illustrates an arrangement 100 for displaying image data via a display device such as an LCD device. The arrangement 100 of FIG. 1 includes an application processor 110 and an LCD module 120. Application processor 110 includes an LCD control 115 providing video signals to LCD module 120. In arrangement 100, the video signals include a video clock signal VCLK, a vertical sync signal VSYNC, a horizontal sync signal HSYNC, a video data enable signal VDEN, and RGB data including eight signals for red R(7:0), eight signals for green G(7:0), and eight signals for blue B(7:0) to provide eight bits for each color. In other embodiments, the RGB data may be arranged differently, for example, a different number of bits for each color, a different number of colors, and/or a different selection of colors. LCD module 120 includes a timing controller 121, a gate (or row) driver 122, a source (or column) driver 123, an LCD panel 124, a back light 125 and a power supply 126.
FIG. 2 shows a functional block diagram of a system 200 for displaying image data via a display device such as an LCD device. System 200 includes a system-on-a-chip (SOC) 210, an LCD module 220 and system memory 230.
In some embodiments, LCD module 220 may be arranged the same as LCD module 120 of FIG. 1.
A system-on-a-chip or SOC refers to a device that integrates all or almost all components of a particular electronic system into a single integrated circuit (chip). It may contain digital, analog, mixed-signal, software, and even radio-frequency functions—all on a single chip substrate. A typical application is in the area of embedded systems.
SOC 210 includes a memory controller 211, a processor (e.g., a general purpose microprocessor, special-purpose processor, digital signal processor, etc.) 212, a clock control block 213, a video port processor 214, and an LCD controller 215 all connected to a common system bus 216. Clock control block 213 may include one or more oscillators, phase-lock loops, etc. for generating one or more clocks or timing signals.
FIG. 3 shows a timing diagram for video signals employed in the system illustrated in FIGS. 1 and 2. The video signals include a vertical sync signal VSYNC, a horizontal sync signal HSYNC, a video data enable signal VDEN, and RGB data RGB_DATA. The top portion of FIG. 3 illustrates one video frame period from one VSYNC pulse to the next VSYNC pulse. The bottom portion of FIG. 3 shows an “exploded view” of one line period within the video frame period, where a line period extends from one HSYNC pulse to the next HSYNC pulse. It should be understood that while FIG. 3 illustrates one signal for RBG_DATA, in practice this represents many parallel signals (e.g., 8 bits/color*3 colors=24 signals in parallel).
As shown in FIG. 3, each video frame period includes an active frame period VACT corresponding to lines of valid RGB data to be displayed by the LCD device. Each video frame period also includes a vertical sync interval (VS), a back porch period (VB), and a front porch period (VF), during each of which periods the video data enable signal VDEN is deactivated or LOW so that no RGB data is displayed by the LCD device. As also shown in FIG. 3, each line period includes an active line period HACT corresponding to valid RGB data to be displayed by the LCD device. The video data enable signal VDEN is enabled (active-HIGH) coincidental with valid RGB data within each active line period HACT so that the valid RGB data is displayed by the LCD device. As also shown in FIG. 3, each line period also includes a horizontal sync interval (HS), a horizontal blanking period (HB), and a horizontal blanking period (HF), during each of which periods the video data enable signal VDEN is deactivated or LOW so that no video data signal is displayed by the LCD device.
In some applications, it is desired or necessary to split image data between two or more display devices. More specifically, in some cases it is desired to split a particular image (including, for example a moving image or video) into two or more portions that are displayed on two or more corresponding LCD devices. For example, it may be desired to display an image with a larger display size than can be practically realized with a single LCD panel.
Unfortunately, this can present some problems since the video data distribution to the plural PCD devices needs to be coordinated and properly timed. If an SOC includes multiple display controllers to control multiple LCD devices, then this increases the chip area that is consumed with the video controlling functionality. Furthermore, as shown above, each LCD module needs to receive a relatively large number of video data and timing signals, and if there are multiple video controllers, then this increases the number of output pins required for the SOC.
Accordingly, it would be desirable to provide a new method and device for driving a plurality of display devices (e.g., LCD devices) that can address one or more of these shortcomings.